1. Field of the Invention
The present invention relates to a process for making capacitor-under-bit-line dynamic random access memory (DRAM) device structures having an improved capacitor top plate design, and more specifically the process employs a novel mask design and a sequence of novel process steps for improving the overlay margin between the bit-line contacts and the capacitors top plates. This method allows the capacitors top plate to be auto-self-aligned to the bit-line contact for increased memory cell density.
2. Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronics industry for storing date. The DRAM circuit includes an array of memory cells, each cell consisting of a single capacitor and a single transfer transistor. Typically the transfer transistor is a field effect transistor (FET). Binary data (1""s and 0""s) are stored as charge on the capacitors, and the transfer transistor is used to retain the charge. During the read cycle the transfer transistor is used to interrogate the cell by means of bit lines. Two types of memory cells that are commonly used include a cell having a trench capacitor formed in the substrate under the FETs, and a cell having a stacked capacitor that is built over and between FETs. In the fabrication of DRAM circuits having stacked capacitors, the capacitor can be formed over the bit lines, commonly referred to as Capacitors-Over-Bit-lines (COB), or under the bit lines, commonly referred to as Capacitors-Under-Bit lines (CUB). For all of the DRAM structures described above, the number of memory cells on a DRAM chip has increased dramatically over the years, and after the year 2000 the number of cells is expected to exceed 1 Gigabit. This increase is a result of the downsizing of the discrete devices using improved high-resolution photolithography, improved directional plasma etching, and self-aligning techniques, with a resulting increase in circuit density.
Numerous methods of making these higher density DRAM devices have been reported. For example, Jeng et al. in U.S. Pat. No. 5,893,734 describe a method for fabricating CUB DRAMs using tungsten landing plugs. U.S. Pat. No. 5,837,579 to Fan et al. describes trenched stacked capacitors, but does not address the formation of the bit-line contact. In U.S. Pat. No. 5,700,731 to Lin et al., a method is described for making a crown-shaped capacitor using an edge phase shift mask, but also does not address the bit-line contact/bit-line formation. In U.S. Pat. No. 5,648,291 to Sung a method is describes for making bit-line contacts self-aligned to underlying capacitors using a thin dielectric sidewall in the bit-line contact openings etched through the capacitor. And in U.S. Pat. No. 5,821,140 to Jost et al. a method is described in which the capacitor with annular bit-line contacts are formed concurrently on a substrate.
Although downscaling of devices and self-aligning techniques have dramatically increased the memory cell density on DRAM chips, there is still a strong need in the industry to further improve the structure and process to provide a more reliable, process with further increase in cell density. More specifically, it is highly desirable to improve the overlay margins between the capacitors and the bit-line contacts.
A principal object of the present invention is to form an array of closely spaced dynamic random access memory (DRAM) cells, with increased overlay margins between capacitor top plates and bit-line contacts resulting in increased memory cell density for Capacitor-Under-Bit line (CUB) DRAM circuits.
Another objective of this invention is to achieve the improved overlay margin by using a novel process and structure resulting in auto-self-aligned capacitor top plates to the bit-line contact to form an improved memory cell structure.
This novel memory cell structure consists of an array of stacked capacitors under bit lines that have an improved overlay margin between the bit-line contacts and the capacitor top electrodes. The method for making the array of memory cells begins by providing a semiconductor substrate having partially completed DRAM devices. The substrate is single-crystal-silicon doped with a P type conductive dopant, such as boron (B). Shallow trench isolation (STI) regions are formed surrounding and electrically isolating an array of device areas for memory cells on the substrate. To form the STI shallow trenches are etched in the substrate, and the trenches are filled with an insulating material, such as silicon oxide (SiOx), and is polished back to the substrate to form a planar surface. These partially completed DRAMs also include word lines that extend over the device areas to form field effect transistors (FETs). Typically the FETs consist of a thin gate oxide on the device areas, and gate electrodes formed from a patterned polycide layer (word lines). The FETs also have source/drain areas, one on each side and adjacent to the FET gate electrodes.
A relatively thin conformal silicon nitride (Si3N4) barrier layer is formed over the device areas and over the STI regions to insulate the FET devices on the DRAM circuit. A first insulating layer is deposited on the substrate, and conducting first and second plug contacts are formed concurrently in the first insulating layer to contact the source/drain areas of the FETs. The conducting first plug contacts extend through the first insulating layer to the first source/drain areas for capacitors, and the conducting second plug contacts extend through the first insulating layer to the second source/drain areas for bit-line contacts. A second insulating layer is deposited, and first openings are formed in the second insulating layer aligned over the first conducting plug contacts. Capacitor bottom electrodes are formed in the first openings aligned over and contacting the first conducting plug contacts. A conformal first conducting layer, such as a doped polysilicon layer, is deposited over the second insulating layer and in the first openings for forming the capacitor bottom electrodes. Additionally, a hemispherical silicon grain (HSG) layer can be formed on the polysilicon layer to increase the surface area for increased capacitance.
A key feature of this invention is to deposit an organic layer sufficiently thick to fill the first openings and to provide an essentially planar top surface. Preferably the organic layer is a photoresist layer. The photoresist layer is patterned to leave portions aligned over the second plug contacts, and to leave portions extending over the edge of the first openings. The patterning is achieved by partially exposing the photoresist through a photomask that has a novel design, and partially developing the photoresist. This patterning results in the photoresist protecting the underlying second insulating layer over the second plug contact (for the bit line), while further recessing the photoresist to expose the first conducting layer elsewhere over the top surface of the second insulating layer. The exposed portions of the first conducting are removed to expose the underlying portions of the second insulating layer. The remaining photoresist is completely removed including the photoresist in the first openings. The exposed portions of the second insulating layer are then selectively and partially etched back to recess those portions below the top portions of the second insulating layer over the second plug contacts. The first conducting layer protects the second insulating layer over the second plug contacts during the selective etching. A thin conformal interelectrode dielectric layer is formed on the first conducting layer (for bottom electrodes). Next a second conducting layer is deposited sufficiently thick to fill the first openings and to fill the recesses over the second insulating layer. The second and the first conducting layers are polished back to the second insulating layer over the second plug contacts to form the capacitor top plates, which are auto-self-aligned to the second insulating layer over the second plug contacts. The auto-self-align results from the polish-back to the top surface of the second insulating layer. This sequence of process steps and novel structure provides an improved overlay margin between the capacitor and the bit-line contacts that are formed next. A third insulating layer is deposited to electrically insulate the capacitor top electrodes. Second openings for bit-line contacts are etched in the third insulating layer and in the second insulating layer aligned over and etched to the second plug contacts. A third conducting layer is deposited to fill the second openings and is polished or etched back to form bit-line contacts. A fourth conducting layer is deposited and patterned to form bit lines over and contacting the bit-line contacts to complete the array of novel memory cells for the DRAM device.